Cross-coupled gated tunneling diode (XTD)

Static random-access memory (SRAM) has important applications as on-chip cache memory in microprocessors. However, the scaling of SRAM is slowing down, with a cell size downscaling of only ~5% in TSMC N3 node compared with N5 node, which raises concerns on the “death of Moore’s Law”. Leveraging the negative differential resistance (NDR) of tunnel diode (TD)/resonant tunneling diode (RTD), a compact tunneling-based SRAM (T-SRAM) cell can be built. The SRAM cell consists of one transistor and two tunnel diodes (1T2D), as opposed to six transistors (6T) with CMOS implementation, thus enabling further SRAM scaling (Fig. 1a). However, the large static leakage current of a TD/RTD (as denoted by a low peak-to-valley current ratio (PVCR) that is typically less than 100) renders the idea nonpractical.

To resolve this issue, I have proposed a cross-coupled gated tunneling diode (XTD) that exhibits extremely low leakage current and a PVCR larger than 10⁵ (Fig. 1b) as verified by TCAD simulation, rejuvenating the field of T-SRAM that has been stalled for more than 20 years. We have also experimentally demonstrated a prototype XTD based on a vertical reconfigurable BP TFET that exhibits a PVCR of 11.32 (Fig. 1c).

In the future, we plan to experimentally demonstrate the T-SRAM using 2D material heterojunctions, exploring wider applications of 2D tunneling devices.

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