Cold-source FET (CS-FET)

Cold-source FET (CS-FET) has been recently proposed as a promising candidate for low-power, steep-slope devices. The device structure of a CS-FET is similar to a MOSFET, except that the source is replaced by a cold source (Fig. 1a), in which the number of modes M_S(E) decreases with higher energy E. That is to say, the number of conducting channels decreases with higher energy. Thus, the high-energy carriers are partially or completely cut off (depending on whether a band gap is present in the cold source) due to the low-pass energy filtering of M_S(E), resulting in an effectively “colder” distribution of the carriers injected into the channel, and thus allowing to achieve a steep SS.

Compared with TFET, which also relies on energy filtering to achieve a steep SS, CS-FET has two major differences/advantages: (1) absence of tunneling through a band gap, thus avoiding the I_ON penalty associated with less-than-unity tunneling transmission in TFETs; (2) the energy filtering in the cold source being independent of the gate control of the potential barrier in the channel, thus resolving a common issue in TFETs that the energy filtering effect (and thus SS) continuously deteriorating due to a widened tunneling window close to the on-state of the device. Simulation of Dirac-source FET (DS-FET, a variant of CS-FET with graphene as cold source) with MoS₂ channel (Fig. 1b) shows a steep SS of 37 mV/dec and a large I_ON>200 μA/μm at V_DD=0.4V (Fig. 1c), highlighting the potential of CS-FET as a steep-slope transistor.

We have studied the design considerations of 2D DS-FET (Fig. 2a), including: (1) doping of graphene Dirac-source; (2) Schottky barrier height; (3) effective mass; (4) disorder in graphene Dirac-source; (5) rethermalization. We have also proposed an alternative mechanism (Fig. 2b) for the steep-slope switching in 1D carbon nanotube (CNT) DS-FET. Please refer to our papers for more details.

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