Field Programmable Gate Array Counter Design

My Role

• • Designed a timer and a calculator that can perform adding and subtraction for eight bit signed interger in Verilog.
• • Combined timer and calculator design with debouncing function and student ID rolling enabled as enhanced feature.
• • Synthesized Verilog code in Xilinx ISE and deployed hardware design on Xilinx Spartan 3e-500 board using JTAG interface.

FPGA Calculator Demonstration

FPGA Counter Demonstration

Documentation

Time and Location

May. 2013 - Aug. 2013

Shanghai Jiao Tong Universith, Shanghai, China

Team Members

Fangzhou Xia, Jiong Xue