In 2006 Multicore processing entered the mainstream. The DoD High
Performance Embedded Computing (HPEC) community has been wrestling with
the programming challenges presented by multicore computing for several
years. The HPEC community got its first taste of multicore computing
in 2001 via Bob Graybill's DARPA Polymorphous Computing Architecture
program. PCA allowed a number of teams to get hands on experience with
the 16 core chip developed by the MIT
team (led by Prof. Anant Agarwal). Early experiences with this and other
clearly demonstrated the enormous performance/Watt potential of
multicore processors, as well as the large programming difficulties. In
response, the HPEC Software Initiative
made a number of research investments to prepare the way for integrating
multicore processors into the Vector, Signal and Image Processing
open software standard. These research projects included efforts to
(led by Richard Linderman of AFRL and Miriam Leeser at Northeastern),
(led by Dan Campbell of GTRI), and the development of
(led by CodeSourcery). In addition, MIT Lincoln Laboratory
developed several multicore technologies in the context of Grid
computing. These included
(led by Hahn Kim) and
Automated Parallel Mapping
(led by Nadya Bliss).
This research has led to the development by Lincoln of the Parallel
Vector Tile Optimizing Library (PVTOL). The PVTOL project (led by
Jeremy Kepner) has two goals
Create a library that allows multicore processors to be quickly
programmed for real signal processing applications.
Develop prototype multicore VSIPL extensions for possible adoption
by the VSIPL standards body.
The first real PVTOL applications are expected to be running in late
2007 or early 2008 using the IBM Cell processor on Mercury Computer
systems. Lincoln is making available the PVTOL Architecture
[PowerPoint ~12 MB][PDF ~6 MB]
to the broader community to encourage the open discussion of the programming
challenges and possible solutions presented by multicore processors.
The main features of PVTOL are
Parallel VSIPL++ look and feel: scalable, portable, high performance.
Automated Parallel Mapping.
Heterogeneous Processors Dispatch Mechanism
This work was sponsored by the Department of Defense under Air Force
Contract FA8721-05-C-0002. Opinions, interpretations, conclusions and
recommendations are those of the authors and are not necessarily
endorsed by the United States Government.
MIT Lincoln Laboratory is a federally funded research and development
center operated by the Massachusetts Institute of Technology under a
contract with the U.S. Air Force. Serving multiple sponsors, the
Laboratory conducts advanced R&D for national defense, with particular
emphasis on advanced electronics and transfers technology to both
government and industry.