Vivienne Sze

Education

Massachusetts Institute of Technology
Ph.D. in Electrical Engineering and Computer Science (expected Spring 2010)
S.M. in Electrical Engineering and Computer Science (June 2006)
Certificate, Financial Technology Option (FTO) at Sloan School of Management (June 2007)

University of Toronto
Bachelor of Applied Science in Electrical Engineering (June 2004)

Research Interests

I am a doctoral candidate in the Digital Integrated Circuits and Systems Group led by Professor Anantha P. Chandrakasan, part of the Microsystems Technology Laboratory at MIT. My research interests include low-power circuit and system design, and low-power algorithms for video compression.

Projects
UWB Baseband

A 50Mb/s UWB Prototype Transceiver
with Nathan Ackerman, Raul Blazquez, Kyle Gilpin, Brian Ginsburg, Fred Lee, and David Wentzloff
August 2005

This prototype transceiver is built using discrete components. It communicates in a 500MHz band centered at 5.355GHz using BPSK pulses with a pulse repetition frequency of 50MHz. The received signal is down-converted to I/Q baseband signals using off-the-shelf discrete components. The baseband signals are digitized by dual 8-bit Atmel ADCs. Synchronization and demodulation are implemented in a Xilinx Virtex II FPGA enabling real-time communication at 50Mb/s. The transceiver communicates with a PC over USB2.0. Real-time one-way transmission of a video stream over the air has been demonstrated at a 50Mb/s raw data rate using this transceiver.

Please visit the Ultra-Wideband Project website for more info.
UWB Baseband

Ultra-Low Voltage UWB Baseband Processor
September 2006

The baseband processor performs acquisition and demodulation of an UWB packet with a throughput of 500-MS/s for a data-rate of 100-Mb/s. It operates at an ultra-low supply voltage of 400-mV to achieve 20 pJ/bit, and utilizes a highly parallelized architecture (with 620 complex correlators) to meet throughput constraints. It was fabricated in a standard-VT 90-nm CMOS process.

Winner, 2007 Design Automation Conference (DAC)/ International Solid-State Circuits Conference (ISSCC) Student Design Contest

Please visit the Sub-Threshold Circuits Group website for more info.
Video decoder

Low Power H.264/AVC Video Decoder
with Daniel Finchelstein and Mahmut Ersin Sinangil
April 2008

The H.264/AVC Baseline Level 3.2 decoder was design in 65-nm CMOS. It can operate at 0.7 V for high definition (720p, 30 fps) video decoding and with a measured power of 1.8 mW, which is over an order of magnitude lower than previously published results. Power reduction is achieved through architectural optimizations such as increased parallelism, multiple voltage / frequency domains and custom voltage-scalable SRAMs.

Outstanding Design Award, 2008 Asian Solid-State Circuits Conference Student Design Contest

Please visit the Portable Multimedia Group website for more info.

Real-time HD Video Decoding System Demo
Get the Flash Player to see this player.
 Video decoder System
Description of video (above)
  1. High definition 720p mobcal sequence playback at 30 frames per second.
  2. PCB with H.264/AVC decoder test chip (black square socket in center).
    Decoded video goes through ribbon cables to VGA socket to LCD display.
  3. Clock signals on scope: Top (yellow) is the core 14 MHz clock.
    Bottom (blue) is the memory controller 50 MHz clock.
  4. Core domain consumes <1mW from a 0.73 V power supply.
  5. Real-time 720p 30fps, H.264/AVC video playback system.

Low Power Video Coding Algorithms for Next Generation Video Coding Standard

Currently developing algorithms for next generation video coding standard 'H.265'. These algorithms have enhanced parallelism to enable low power architectures and improved coding-efficiency vs. power trade-off.

Publications

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Ultra-Wideband

Low Power H.264/AVC Video Decoder

Low Power Video Coding Algorithms for Next Generation Video Coding Standard

ITU-T VCEG (Video Coding Experts Group) Standards Body Contributions

  • V. Sze and M. Budagavi, "Massively Parallel CABAC Cross-Verification," ITU-T Q.6/SG16 VCEG, COM-16-C-227-E, Geneva, October 2009.

    *The MP-CABAC has been adopted by VCEG into the KTA software.

  • V. Sze. M. Budagavi, and A. P. Chandrakasan, "Massively Parallel CABAC," ITU-T Q.6/SG16 VCEG, VCEG-AL21, Geneva, July 2009.

  • V. Sze, M. U. Demircin and M. Budagavi, "CABAC throughput requirements for real-time decoding," ITU-T Q.6/SG16 VCEG, VCEG-AJ31, San Diego, October 2008.

  • V. Sze and M. Budagavi, "Parallel CABAC," ITU-T Q.6/SG16 VCEG, COM-16-C-334-E, Geneva, April 2008.

Awards

  • Outstanding Design Award, 2008 Asian Solid-State Circuits Conference Student Design Contest "A Low Power 0.7-V H.264 Video Decoder", by Daniel Finchelstein, Vivienne Sze, Mahmut Ersin Sinangil, Yildiz Koken, Anantha P. Chandrakasan.

  • Presentation Award, 2008 MTL Annual Research Conference (MARC) "Algorithms and Architectures for Low Power Video Coding" by Vivienne Sze

  • Winner, 2007 Design Automation Conference (DAC)/ International Solid-State Circuits Conference (ISSCC) Student Design Contest "Design of an Ultra-Low-Voltage UWB Baseband Processor" by Vivienne Sze and Anantha P. Chandrakasan.



Last Updated: November 7, 2009