Rahul Rithe

Resume

Ph.D. candidate in Electrical Engineering and Computer Science at Massachusetts Institute of Technology.

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Education

  • Ph.D. : Massachusetts Institute of Technology [June 2010 - Present]

    • Electrical Engineering and Computer Science

  • S.M. : Massachusetts Institute of Technology [September 2008 - June 2010]

    • Electrical Engineering and Computer Science
    • GPA: 5.0/5.0
    • Thesis: SSTA Design Methodology for Low-Voltage Operation
    • Ernst A. Guillemin award for best S.M. thesis in Electrical Engineering

  • B.Tech. (Honors) : Indian Institute of Technology Kharagpur [August 2004 - June 2008]

    • Electronics and Electrical Communication Engineering
    • GPA: 9.69/10
    • Thesis: Design and Implementation of Serializer-Deserializer for High-Speed Wired Link
    • Best B. Tech. Thesis Award
    • President of India Gold Medal for best academic performance in the class of 2008

Journal Publications

  • R. Rithe, C. C. Cheng, A. Chandrakasan, "Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding ," IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 11, 2724-2736, November 2012.

  • M. E. Sinangil, M. Yip, M. Qazi, R. Rithe, J. Kwong, A. Chandrakasan, “Design of Low-Voltage Building Blocks and ADCs for Energy-Efficient Systems,” IEEE Transactions on Circuits and Systems (TCAS) II: Express Briefs, Vol. 59, No. 9, 533-537, September 2012.

  • R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, "The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 5, 911-924, May 2012.

  • N. Ickes, G. Gammie, M. E. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Honnavara-Prasad, L. Ho, G. Baldwin, D. Buss, A. P. Chandrakasan, U. Ko, "A 28 nm 0.6 V Low Power DSP for Mobile Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 1, 35-46, January 2012.

Conference Publications

  • R. Rithe, P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, "Reconfigurable Processor for Energy-Scalable Computational Photography," IEEE International Solid-State Circuits Conference (ISSCC), 164-165, February 2013.

  • R. Rithe, C. C. Cheng, A. Chandrakasan, "Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding ," IEEE Asian Solid-State Circuits Conference (A-SSCC), 401-404, November 2011.

  • G. Gammie, N. Ickes, M. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Honnavara-Prasad, L. Ho, G. Baldwin, D. Buss, A. Chandrakasan, U. Ko, "A 28nm 0.6V Low-Power DSP for Mobile Applications," IEEE International Solid-State Circuits Conference (ISSCC), 132-133, February 2011.

  • R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, "Cell Library Characterization at Low Voltage using Non-Linear Operating Point Analysis of Local Variations," International Conference on VLSI Design, 112-117, January 2011.

  • R. Rithe, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, "Non-Linear Operating Point Statistical Analysis for Local Variations in Logic Timing at Low Voltage," Design, Automation and Test in Europe (DATE) Conference, 965-968, March 2010.

Research Experience

  • Reconfigurable Processor for Computational Photography, MIT [January 2011 - May 2012]

    • Computational photography applications enable capture and synthesis of images that could not be captured with a traditional camera. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations to allow real-time processing. This work implements a reconfigurable multi-application processor to enable energy-efficient real-time computational photography on portable multimedia devices.

  • Multi-Standard Low-Power Video Encoding, MIT [September 2009 - December 2010]

    • Designing a reconfigurable video encoder supporting H.264/AVC High Profile and VC-1 Advanced Profile video coding standards with 4kx2k resolution at 30fps, implemented on a single low-power ASIC. The work explores algorithmic, architectural, and circuit-level innovations that can be applied to each of the functional blocks in a multi-standard video encoder to enable low-voltage operation while maintaining performance.

  • SSTA Design Methodology for Low Voltage Operation, MIT [September 2008 - April 2010]

    • Developing a computationally efficient methodology for stochastic characterization of standard cell libraries, timing path analysis and full-chip timing closure at low voltage operation. Implementation of the timing analysis methodology using commercial CAD tools and integration into a commercial IC design flow.

  • Timing and Power Characterization for Asynchronous Circuits, USC [May - July 2007]

    • Developing a characterization methodology that supports back-annotated power and timing for high-performance asynchronous circuits based on the Static Single-Track Full-Buffer Template.

  • SerDes for High Speed Wired Link, IIT Kharagpur [December 2006 - April 2008]

    • Design and implementation of a low power serializer-deserializer for high-speed data transmission over wired link using current mode signaling.

Industry Experience

  • Texas Instruments - Systems and Applications R&D Center, Dallas, TX [June - July 2012]

    • Systems Engineering Intern: Development of efficient system architecture through algorithm-architecture co-design for computational photography applications using camera sensor arrays in mobile devices.

  • Texas Instruments - Wireless Terminal Business Unit, Dallas, TX [July - August 2010]

    • WTBU Intern: Implementation of SSTA Timing Closure Methodology for ICs operating at Low Voltage. Implemented the SSTA approach using commercial CAD tools and integrated into IC design flow. Demonstrated the approach on a DSP IC.

  • Texas Instruments - Wireless Terminal Business Unit, Dallas, TX [June - August 2009]

    • WTBU Intern: Statistical Static Timing Analysis at Ultra-Low Voltage Operation. Developed an approach for standard cell library characterization and timing path analysis at ultra-low voltage in presence of global and local variations.

Teaching Experience

  • Preparation for Undergraduate Research (6.UAR), MIT [Spring 2013]

  • Circuits and Electronics (6.002), MIT [Fall 2012]

  • Short-Term Course on VLSI Design, IIT Kharagpur [October 2007]

Term Projects / Seminars

  • Project: A Low Power Oscillator with Feedback Amplitude Regulation [December 2009] [Slides PDF]

  • Project: Implementation of an Adaptive Equalizer using LMS Algorithm and a Digital Filter in TMS320C6711 DSP kit [April 2007]

  • Seminar: Semiconductor Devices and Applications - Back End Processes [December 2006]

Scholastic Achievements

  • MTL Annual Research Conference Presentation Award. [January 2013]

  • Ernst Guillemin Award for Best S.M. Thesis in Electrical Engineering, MIT. [May 2010]

  • Irwin Mark Jacobs and Joan Klein Jacobs Presidential Fellowship for Graduate Studies, MIT. [2008 - 2009]

  • President of India Gold Medal for best academic performance in the class of 2008, IIT Kharagpur. [54th Convocation, 2008]

  • Best B.Tech. (H) Thesis Award, IIT Kharagpur. [54th Convocation, 2008]

  • InfoUSA Summer Research Fellowship 2007, USC. [May - July 2007]

  • National Talent Search Scholarship by National Council of Educational Research and Training, India. [2002]