I received a Ph.D. in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology (MIT) in 2014. I worked in the Energy-Efficient Circuits and Systems Group headed by Prof. Anantha Chandrakasan. My Ph.D. thesis focused on 'Energy-Efficient System Design for Mobile Processing Platforms' through system level innovations, including algorithm, architecture and circuit co-design.
I received my S.M. degree in Electrical Engineering and Computer Science from MIT in 2010. As part of my S.M. thesis, I worked on developing a 'SSTA Design Methodology for Low Voltage Operation'. For this work, I was awarded the Ernst A. Guillemein Award for best S.M. thesis in Electrical Engineering by the Department of Electrical Engineering and Computer Science at MIT.
I completed my undergraduate degree, B.Tech. (Honors), in Electronics and Electrical Communication Engineering from Indian Institute of Technology (IIT) Kharagpur, India, in 2008. While at IIT Kharagpur, I worked with Prof. Pradip Mandal on High Speed Serializer-Deserializer Design. I was awarded the President of India Gold Medal and the best B.Tech thesis award.
I am interested in developing energy efficient systems for multimedia applications in portable devices. Power and battery life have become critical concerns with the ever-increasing use of multimedia applications, such as video playback, on portable devices. I am interested in exploring power reduction techniques at various stages of the design, including algorithms, architectures and circuits.
R. Rithe, P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, "Reconfigurable Processor for Energy-Scalable Computational Photography," IEEE International Solid-State Circuits Conference (ISSCC), 164-165, February 2013.
R. Rithe, C. C. Cheng, A. Chandrakasan, "Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding ," IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 11, 2724-2736, November 2012.
R. Rithe, S. Chou, J. Gu, A. Wang, S. Datla, G. Gammie, D. Buss, A. Chandrakasan, "The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 20, No. 5, 911-924, May 2012.
N. Ickes, G. Gammie, M. E. Sinangil, R. Rithe, J. Gu, A. Wang, H. Mair, S. Datla, B. Rong, S. Honnavara-Prasad, L. Ho, G. Baldwin, D. Buss, A. P. Chandrakasan, U. Ko, "A 28 nm 0.6 V Low Power DSP for Mobile Applications," IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 1, 35-46, January 2012.
MIT Microsystems Technology Laboratory 50 Vassar Street, 38-107 Cambridge, MA 02139