module cnt32 (CLK, Q, CLR) ;

input CLK ;
output [31:0] Q ;
input CLR ;

reg [31:0] count;

always @(posedge CLK)
begin
   if (CLR)
      count = 31'b0;
   else begin
      count = count + 1;
  end
end

assign Q = count;

// add your code here

endmodule